In communication systems, FSK (frequency-shift-keying) modulation/demodulation systems are often used to modulate a digital signal (like 0 and 1) at transmitting terminals into an analog signal with two kinds of frequencies (like f0 and f1), and demodulate the modulated analog signal with such two kinds of frequencies at receiving terminals back to a recovered digital signal, so that the data enclosed in the modulated analog signal can be distinguished. In such modulation/demodulation systems, since the alternation frequency of the inputted digital signal between logic 0's and 1's is very fast, high-frequency noise at transmitting terminals may occur.
Therefore, GFSK modulation/demodulation systems have been designed as FIG. 1 (Prior Art) to reduce high-frequency noise introduced in conventional FSK modulation/demodulation systems. In GLPF modulation systems, an digital signal Data.sub.-- in (like 0 and 1) is first input to a Gaussian low-pass filter GLPF to obtain a frequency control word FCW, which is smoother than the inputted digital signal Data.sub.-- in and is represented by a plurality of bits according to the Gaussian low-pass filtter GLPF. The frequency control word FCW then is inputted to a direct digital frequency synthesizer DDFS to obtain a corresponding digital sine signal Sin.sub.-- out, which is outputted through the D/A converter DAC as the modulated analog sine signal Sin.sub.-- wave.
The advantages of GFSK modulation systems are:
1. A constant envelope;
2. A narrow power spectrum; and
3. Non-coherent detection.
FIG. 2 (Prior Art) is a circuit diagram of a conventional direct digital frequency synthesizer DDFS. The direct digital frequency synthesizer comprises an accumulator Acc, a sine ROM, a digital-to-analog converter DAC and a low-pass filter LPF, wherein the accumulator Acc is used to sequentially output a sample address ADDRESS according to a frequency control word FCW. The sample address ADDRESS and the frequency control word FCW can be respectively represented by L bits. The sine ROM is looked up according to the sample address ADDRESS and a corresponding digital sine signal Sin.sub.-- is outputted. Then, the digital sine signal Sin.sub.-- is output through the digital-to-analog converter DAC and the low-pass filter LPF to obtain a corresponding analog sine signal Sin.sub.-- wave and the modulated output Vo. In this case, since the sine signal has been digitized, the direct digital frequency synthesizer DDFS can avoid such problems as the ageing of components, frequency deviation, high-frequency noise interference, and can easily achieve better communication quality, interference robustness, anti-eavesdrop and extra functions. In addition, the relative phase and sign of each node in GFSK modulation/demodulation systems are also shown in FIG. 2.
However, the size of the direct digital frequency synthesizer DDFS is large because of the sine ROM. Generally, in order to reduce high-frequency noise in the direct digital frequency synthesizer DDFS, the frequency control word FCW is often represented by 16 or more bits. That is, there are 2.sup.16 sine signal samples stored in the sine ROM, therefore, as the size of the sine ROM increases high-frequency noise is reduced.
Consequently, most conventional direct digital frequency synthesizers utilize various kinds of decompositions of the sine function to reduce the number of the stored sine signal samples to thereby reduce the size of the sine ROM.
FIG. 3 (Prior Art) is a circuit diagram of another conventional direct digital frequency synthesizer using the symmetry property of the sine function. Differing from the direct digital frequency synthesizer of FIG. 2, the sample address ADDRESS outputted from the accumulator Acc is first transmitted to a symmetry circuit SYMMETRY before being transmitted to the sine ROM, and, the digital sine signal Sin.sub.-- out is first transmitted to a sign circuit SIGN before being transmitted to the digital-to-analog converter DAC.
Often, the symmetry circuit SYMMETRY is an XOR gate controlled by a clock CLOCK1 the period of which is twice that of the first MSB of the sample address ADDRESS. Furthermore, the accumulator Acc is designed to have more bits than the sample address ADDRESS. When the accumulator Acc is designed to have 16 bits and the sample address ADDRESS is the last 12 LSBs of the output of the accumulator Acc, the clock CLOCK1 can also be the last 13.sup.th LSB of the output of the accumulator Acc. In addition, the symmetry circuit SYMMETRY, which may be the XOR gate, can then the take 1's (or 2's) complement of the sample address ADDRESS to sequentially output a symmetric sample address ADDRESS' every two period 2T (T is the period of the sample address ADDRESS). That is, the symmetry circuit outputs the sample address in a period and the 1's (or 2's) complement of the sample address in the next period as the symmetric sample address ADDRESS'.
The sign circuit SIGN may be an inverter controlled by a clock CLOCK2 of which the period is four times as the first MSB of the sample address ADDRESS. The clock CLOCK1 can be the last 14.sup.th LSB of the output of the accumulator Acc in this case. And the sign circuit SIGN, which may be the inverter, can alternate the sign of the outputted modulated sine signal corresponding to the symmetric sample address ADDRESS' every four period 4T. That is, the sign circuit SIGN outputs the sign bit "1" (positive) in two periods and the sign bit "0" (negative) in the next two periods as the sign bit of the outputted sine signal Sin.sub.-- out.
FIG. 4 (Prior Art) is a diagram showing the waveform of each node of the direct digital frequency synthesizer as shown in FIG. 3. Wherein, T is the period of the sample address ADDRESS outputted by the accumulator Acc; CLOCK1 is a clock of which the period is twice the period of the first MSB of the sample address ADDRESS; CLOCK2 is a clock of which the period is four times that of the period of the first MSB of the sample address ADDRESS; ADDRESS' is the symmetric sample address outputted from the symmetry circuit SYMMETRY; Sin.sub.-- out' is the output of the sine ROM according to the symmetric sample address ADDRESS' of the symmetric circuit SYMMETRY; and Sin.sub.-- out is the output sine signal from the sign circuit SIGN.
Further, for EQU sin (x)=sin (180.degree.-x), 90.degree.&lt;x&lt;180.degree. EQU sin (x)=-sin (x-180.degree.), 180.degree.&lt;x&lt;360.degree.
the output sine signal Sin.sub.-- out obtained after inserting the symmetry circuit SYMMETRY and the sign circuit SIGN can match both the phase and sign of a real sine function. Therefore, it is necessary to store only 1/4 of the sine signal samples in the sine ROM, effectively reducing the size of the sine ROM.